1. Field of the Invention
The present invention relates to a device for analyzing failure in a semiconductor device, and more particularly to a device for analyzing failure in a semiconductor device provided with an internal voltage generating circuit.
2. Description of the Background Art
In one of the techniques of failure analysis of semiconductor devices, a semiconductor device is scanned with a laser beam, and a light induced current attributable to electron-hole pairs generated in the semiconductor device is measured using a scanning optical microscope. This technique is called an OBIC (Optical Beam Induced Current) method. With a similar technique called a non-bias OBIC method, a semiconductor device is again scanned with a laser beam, and thermal electromotive force that is generated when a material forming the semiconductor device is heated by the laser beam irradiation is measured.
In another technique of failure analysis of semiconductor device, a semiconductor device applied with a bias is scanned with a laser beam to locally heat the semiconductor device, and a change in electric resistance at the heated portion is measured. This technique is called an OBIRCH (Optical Beam Induced Resistance CHange) method. In this method, by application of the bias, the change of electric resistance is detected by presence/absence of current on a wiring or the like of the semiconductor device. The OBIRCH method is disclosed, e.g., in Japanese Patent Laying-Open No. 6-300824.
There is yet another technique similar to the OBIRCH method wherein a semiconductor device applied with a bias is scanned with an infrared (IR) laser beam to locally heat the semiconductor device, and a change in electric resistance at the heated portion is measured. This is called an IR-OBIRCH method. In the IR-OBIRCH method, infrared rays with which electron-hole pairs are not generated in the semiconductor device are used for the laser beam irradiation to suppress generation of a light induced current. The laser beam is used solely as a heat source. The IR-OBIRCH method is disclosed, e.g., in Japanese Patent Laying-Open No. 9-145795.
FIGS. 16-19 are schematic diagrams showing various configurations of a device for conducting the failure analysis of semiconductor device as described above (hereinafter, referred to as the “semiconductor failure analysis device”). As shown in FIGS. 16-19, the configurations of the semiconductor failure analysis device is classified into four types depending on whether the measuring instrument is an amperemeter or a voltmeter, and whether the measuring instrument is connected to a power supply terminal or a ground terminal of the semiconductor device.
The semiconductor failure analysis devices shown in FIGS. 16 and 18 each include a semiconductor device 1 for which failure analysis is conducted, a laser microscope 2 applying light energy or thermal energy to semiconductor device 1, a variable stabilizing power source 3 applying a variable voltage to semiconductor device 1, and an amperemeter 4 measuring a change of a current flowing through semiconductor device 1 at the time of failure analysis. The semiconductor failure analysis devices shown in FIGS. 17 and 19 each include, instead of the amperemeter 4 shown in FIGS. 16 and 18, a voltmeter 5 measuring a change of a voltage being applied across semiconductor device 1 at the time of failure analysis.
FIG. 16 shows the configuration having amperemeter 4 connected to the ground terminal of semiconductor device 1. FIG. 17 shows the configuration having voltmeter 5 connected to the ground terminal of semiconductor device 1. FIG. 18 shows the configuration having amperemeter 4 connected to the power supply terminal of semiconductor device 1, and FIG. 19 shows the configuration having voltmeter 5 connected to the power supply terminal of semiconductor device 1.
In the failure analysis techniques of semiconductor devices as described above wherein a laser beam is employed to measure current change or voltage change occurring in the semiconductor device, the amount of the current or voltage change due to the laser beam irradiation is extremely small. To make such a failure analysis technique applicable to a semiconductor device, it is necessary to keep the semiconductor device in a static state such that the current or voltage being input to amperemeter 4 or voltmeter 5 would not vary because of any other reason but the laser beam irradiation.
However, a semiconductor device provided with an internal voltage generating circuit (e.g., a DRAM (Dynamic Random Access Memory)) cannot be maintained in the static state, as an internal voltage is generated to enable an operation of the semiconductor integrated circuit. In such a device, even if power supply voltage, power supply current, external signal input and others are maintained in the static state, they would vary due to the internal voltage generating operation. Thus, the failure analysis techniques as described above were not applicable to the semiconductor device provided with an internal voltage generating circuit like a DRAM.
FIG. 20 is a schematic diagram of an internal voltage generating circuit 11 provided in a semiconductor device such as a DRAM.
The internal voltage generating circuit 11 shown in FIG. 20 includes a charge pump circuit 6 generating a voltage V on a wiring 7, and a voltage comparison circuit 9 comparing the voltage V on wiring 7 with a reference voltage Vref on a wiring 8. Although the internal voltage generating circuit may generate a positive voltage or a negative voltage, the case where a positive voltage is generated is now described.
Voltage V on wiring 7 and reference voltage Vref on wiring 8 are applied to voltage comparison circuit 9. Voltage comparison circuit 9 compares voltage V with reference voltage Vref, and transmits a control signal f on a wiring 10 to charge pump circuit 6 based on the comparison result. When voltage V is lower than reference voltage Vref, control signal f causes charge pump circuit 6 to operate to generate a higher voltage. When voltage V is equal to or higher than reference voltage Vref, control signal f causes charge pump circuit 6 to stop the operation. As such, voltage V is adjusted to equal the reference voltage Vref.
Voltage V, reference voltage Vref and others generated by internal voltage generating circuit 11 are normally generated from a power supply voltage of the semiconductor device. Thus, as internal voltage generating circuit 11 operates, the power supply voltage and the power supply current would change with amounts that are generally greater than the amount of voltage change or current change due to the laser beam irradiation in the failure analysis technique of semiconductor device as described above.
As such, in the failure analysis of the semiconductor device provided with an internal voltage generating circuit, even if there is a voltage change or current change as the laser beam irradiates a defective portion, such a change would be hidden in the change of power supply voltage or power supply current, hindering detection of the defective portion.
Moreover, even if the voltage change or current change by the laser beam irradiation at the defective portion is unhidden by the change of power supply voltage or power supply current, in the case where a power supply terminal of the semiconductor device is used as a detecting terminal of the voltage change or current change that occurs at the defective portion by the laser beam irradiation, it would be difficult to detect the defective portion if a current consumed by the internal voltage generating circuit is greater than a leakage current at the relevant defective portion.
Furthermore, since the change of power supply voltage or power supply current caused by the operation of the internal voltage generating circuit is asynchronous with the laser beam scanning during the failure analysis of the semiconductor device, it causes a noise, which may lead to misinterpretation of a non-defective portion as a defective portion.